1. Field of the Invention
The present invention generally relates to maintaining variation tolerances of line widths for electronic chip fabrication in sub-100 nm devices. Specifically, a precisely-tuned trimming plasma etch procedure for a first soft mask is followed by a precisely defined oxide hard-mask etch procedure to result in a process that achieves minimum linewidth variation tolerances from the nominal value, not only for the vertical versus horizontal dimension but also for variations between isolated features versus nested features.
2. Description of the Related Art
As features on electronic chips have become smaller, a point is eventually reached in which the conventional process of simply developing a lithographic image projected onto the wafer no longer provides the required Critical Dimension (CD). Critical dimension (or gate line-width) control has become increasingly important for Sub-100 nm devices. At these small feature sizes, not only is it critical to control variations in line widths for a single line, the fabrication must also be able to control variations considering separately the horizontal dimension versus the vertical dimension and variations considering separately the isolated features versus nested features, where nested features would mean, for example, a plurality of tightly pitched lines. Extremely tight across-chip line-width variation (ACLV) tolerances for these devices require that the isolated and nested features be identical in line-widths. In the past generations of conventional logic programs, a fixed line-width trimming process was used with no capability of altering the relative trim rate of isolated and nested features.